The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing an MIS-type semiconductor integrated circuit (IC) device (e.g., an MOS IC) which is constructed of MOS (Metal Oxide Semiconductor) type transistors, for example.
CMOS (Complementary MOS) ICs, each of which has MOS transistors of the two opposite channel conductivity types of P- and N-channels, have such merits as very low power dissipation and high operating speed and are used for various circuits.
As a method for manufacturing the CMOS IC, a method to be stated below has generally been performed. First, a polycrystalline silicon film to become gate electrodes is formed on an N-type silicon semiconductor substrate and a P-type well region formed therein. The P-type well region is selectively covered with a silicon dioxide film (SiO.sub.2 film) formed by chemical vapor deposition (CVD). Using the SiO.sub.2 film as a mask, boron is diffused into the N-type silicon substrate not covered with the SiO.sub.2 film, to form source and drain regions of the P.sup.+ -type. Thereafter, the SiO.sub.2 film is removed, that part of the surface of the N-type silicon semiconductor substrate in which the P-type well region is not formed is selectively covered with an SiO.sub.2 film formed by CVD anew, and using this SiO.sub.2 film as a mask, phosphorus is diffused into the surface of the P-type well region so as to form source and drain regions of the N-type. The SiO.sub.2 film formed by CVD and used as the mask at the diffusion of phosphorus is removed. A new SiO.sub.2 film as a passivation film is formed on the whole surface of the substrate by CVD. Contact holes are formed in the new SiO.sub.2 film, and an Al film is evaporated on the whole surface and subsequently formed into Al electrodes by photolithography.
This method, however, has been found to incur the following problem by the inventors. When the SiO.sub.2 film formed by CVD is removed by etching, the underlying field SiO.sub.2 film is also etched partly. Consequently, a step arises in the surface of the field SiO.sub.2 film. In case of forming Al wiring or the like over the field SiO.sub.2 film, there is posed the problem that the Al wiring is liable to break at the step. The breakage of the Al wiring occurs noticeably particularly when the wiring of a polycrystalline silicon film is formed on the field SiO.sub.2 film. The reason is that, when the SiO.sub.2 film formed by CVD is etched, the field SiO.sub.2 film under the wiring of the polycrystalline film is side-etched (under-etched), so that the step of the field SiO.sub.2 film surface in this part (the distance from the surface of the wiring of the polycrystalline silicon film to the side-etched surface of the field SiO.sub.2 film) becomes more abrupt (longer). Therefore, the breakage of the Al wiring due to the step is more liable to take place.
On the other hand, in recent years, researches have been made on the application of a double layer structure of polycrystalline silicon films to a CMOS IC. The inventors studied and produced a CMOS IC of the double layer structure by the use of the conventional manufacturing method described above. As a result, they encountered problems to be stated below. The second layer of polycrystalline silicon film deposited over the step part of the surface of the field SiO.sub.2 film as described above is not sufficiently removed when etched in order to photolithographically work it into a predetermined pattern. Due to the deposited polycrystalline silicon film, a leakage current flows between the wiring leads of the second layer (level) of polycrystalline silicon film. As a measure for solving the problem, it is possible to render the wiring pitches of the polycrystalline silicon film large. This measure, however, requires a large wiring area and results in hampering enhancement in the density of integration.
Further, in manufacturing the CMOS IC which has the double-layer structure of the polycrystalline silicon films, the problem of a complicated process is involved when the conventional method of manufacturing the CMOS IC as described above is performed as it is. The reason is that, as explained before, the SiO.sub.2 films formed by CVD are respectively used as the masks in the step of forming the N.sup.+ -type source and drain regions and the step of forming the P.sup.+ -type source and drain regions, and besides these SiO.sub.2 films which serve as the masks, a new SiO.sub.2 film formed by CVD is used as the inter-layer insulator film between the first layer of polycrystalline silicon film and the second layer of polycrystalline silicon film.